Spacer-confined epitaxial growth
US10978573B2 · kind B2 · utility
1Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2019 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | Jul 8, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0133
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Semiconductor devices and methods of forming the same include forming a dummy gate on a stack of alternating channel layers and sacrificial layers. A spacer layer is formed over the dummy gate and the stack. Portions of the spacer layer on horizontal surfaces of the stack are etched away to form vertical spacers. Exposed portions of the stack are etched away. Semiconductor material is grown from exposed sidewalls of remaining channel layers to form source and drain structures that are constrained in lateral dimensions by the vertical spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.