Structure and method to improve FAV RIE process margin and Electromigration
US10985056B2 · kind B2 · utility
1Cited by
3References
4Claims
0Family size
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Key dates
| Filing date | Dec 22, 2017 |
| Grant date | Apr 20, 2021 |
| Priority date | — |
| Expiry date | Dec 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76883
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming fully aligned vias in a semiconductor device, the method including recessing a first level interconnect line below a first interlevel dielectric (ILD), laterally etching the exposed upper portion of the first interlevel dielectric bounding the recess, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.