Electronic package that includes lamination layer
US10985080B2 · kind B2 · utility
0Cited by
1References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2015 |
| Grant date | Apr 20, 2021 |
| Priority date | — |
| Expiry date | Dec 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic package that includes a substrate and an electronic component attached to the substrate. A laminated layer is attached to an upper surface of the substrate such that the laminated layer covers the electronic component. The electronic package may further include a stiffener mounted on the laminated layer where the stiffener is over the electronic component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.