Semiconductor package and manufacturing method thereof
US10985115B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2020 |
| Grant date | Apr 20, 2021 |
| Priority date | — |
| Expiry date | Jun 19, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first redistribution structure, a semiconductor die electrically coupled to the first redistribution structure, a die attach material interposed between the first redistribution structure and the semiconductor die, and an insulating encapsulant disposed on the first redistribution structure and covering the semiconductor die and the die attach material. A bottom of the semiconductor die is embedded in the die attach material, and a thickness of a portion of the die attach material disposed over a spacing of conductive traces of the first redistribution structure is greater than a thickness of another portion of the die attach material disposed over the conductive traces of the first redistribution structure and underlying the bottom of the semiconductor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.