Power side-channel attack resistant advanced encryption standard accelerator processor
US10985903B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2018 |
| Grant date | Apr 20, 2021 |
| Priority date | — |
| Expiry date | Dec 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/24
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A processing system includes a processing core and a hardware accelerator communicatively coupled to the processing core. The hardware accelerator includes a random number generator to generate a byte order indicator. The hardware accelerator also includes a first switching module communicatively coupled to the random value indicator generator. The switching module receives an byte sequence in an encryption round of the cryptographic operation and feeds a portion of the input byte sequence to one of a first substitute box (S-box) module or a second S-box module in view of a byte order indicator value generated by the random number generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.