Raghavan Kumar
63Patents
6h-index
35Co-inventors
64Inventor score
Filing activity: Apr 1, 2016 → Aug 24, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10642922B2 | Binary, ternary and bit serial compute-in-memory circuits | Physics | 15 | Active |
| US11048434B2 | Compute in memory circuits with time-to-digital computation | Physics | 9 | Active |
| US10860682B2 | Binary, ternary and bit serial compute-in-memory circuits | Physics | 8 | Active |
| US10922607B2 | Event driven and time hopping neural network | Physics | 8 | Active |
| US11061646B2 | Compute in memory circuits with multi-Vdd arrays and/or analog multipliers | Physics | 7 | Active |
| US10748603B2 | In-memory multiply and accumulate with global charge-sharing | Physics | 7 | Active |
| US10825509B2 | Full-rail digital read compute-in-memory circuit | Physics | 5 | Active |
| US10831446B2 | Digital bit-serial multi-multiply-and-accumulate compute in memory | Physics | 4 | Active |
| US10565138B2 | Memory device with multiple memory arrays to facilitate in-memory computation | Emerging Cross-Sectional Technologies | 3 | Active |
| US10877752B2 | Techniques for current-sensing circuit design for compute-in-memory | Physics | 2 | Active |
| US10713558B2 | Neural network with reconfigurable sparse connectivity and online learning | Physics | 2 | Active |
| US11151046B2 | Programmable interface to in-memory cache processor | Physics | 2 | Active |
| US11405213B2 | Low latency post-quantum signature verification for fast secure-boot | Electricity | 2 | Active |
| US11303429B2 | Combined SHA2 and SHA3 based XMSS hardware accelerator | Electricity | 2 | Active |
| US11138499B2 | Applications of back-end-of-line (BEOL) capacitors in compute-in-memory (CIM) circuits | Physics | 2 | Active |
| US11416165B2 | Low synch dedicated accelerator with in-memory computation capability | Emerging Cross-Sectional Technologies | 1 | Active |
| US10754619B2 | Self-calibrated von-neumann extractor | Electricity | 1 | Active |
| US10635404B2 | Mixed-coordinate point multiplication | Electricity | 1 | Active |
| US10884957B2 | Pipeline circuit architecture to provide in-memory computation functionality | Emerging Cross-Sectional Technologies | 1 | Active |
| US11218320B2 | Accelerators for post-quantum cryptography secure hash-based signing and verification | Electricity | 1 | Active |
| US10985903B2 | Power side-channel attack resistant advanced encryption standard accelerator processor | Electricity | 1 | Active |
| US10360496B2 | Apparatus and method for a digital neuromorphic processor | Physics | 1 | Active |
| US10825511B2 | Device, system, and method to change a consistency of behavior by a cell circuit | Physics | 1 | Active |
| US11726950B2 | Compute near memory convolution accelerator | Emerging Cross-Sectional Technologies | 1 | Active |
| US10705967B2 | Programmable interface to in-memory cache processor | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.