Memory with automatic background precondition upon powerup
US10990317B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2019 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Aug 28, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices and systems with automatic background precondition upon powerup, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a plurality of memory cells at intersections of memory rows and memory columns. The memory device further includes sense amplifiers corresponding to the memory rows. When the memory device powers on, the memory device writes one or more memory cells of the plurality of memory cells to a random data state before executing an access command received from a user, a memory controller, or a host device of the memory device. In some embodiments, to write the one or more memory cells, the memory device fires multiple memory rows at the same time without powering corresponding sense amplifiers such that data stored on memory cells of the multiple memory rows is overwritten and corrupted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.