Multi-power-domain bridge with prefetch and write merging
US10990529B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2019 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Nov 1, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for accessing data, comprising receiving a first memory request associated with a first clock domain, converting a first memory address of the first memory request from a first memory address format associated with the first clock domain to a second memory address format associated with the second clock domain, transitioning the first memory request to a second clock domain, creating a first scoreboard entry associated with the first memory request, transmitting the first memory request to a memory based on the converted first memory address, receiving a first response to the first memory request, transitioning the first response to the second clock domain and clearing the first scoreboard entry based on the received response.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.