System and method for incremental topology synthesis of a network-on-chip
US10990724B1 · kind B1 · utility
18Cited by
3References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2019 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Dec 27, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed synthesis of network, such as a network-on-chip (NoC). The network is initially synthesized. In accordance with various embodiments and aspects of the invention, a tool is used to synthesize and generate the NoC from a set of constraints. The tool produces consistent results between different synthesis runs, which have slight varying constraints.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.