Method of improving read current stability in analog non-volatile memory by limiting time gap between erase and program
US10991433B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2020 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Feb 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6892
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device having non-volatile memory cells and a controller. In response to a first command for erasing and programming a first group of the memory cells, the controller determines the first group can be programmed within substantially 10 seconds of their erasure, erases the first group, and programs the first group within substantially 10 seconds of their erasure. In response to a second command for erasing and programming a second group of the memory cells, the controller determines that the second group cannot be programmed within substantially 10 seconds of their erasure, divides the second group into subgroups of the memory cells each of which can be programmed within substantially 10 seconds of their erasure, and for each of the subgroups, erase the subgroup and program the subgroup within substantially 10 seconds of their erasure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.