Method for controlling transistor delay of nanowire or nanosheet transistor devices
US10991626B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2020 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Jun 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes: a substrate having a planar surface; a first gate-all-around field effect transistor (GAA-FET) provided on said substrate and comprising a first channel having an untrimmed volume of first channel material corresponding to a volume of the first channel material within a first stacked fin structure from which the first channel was formed; and a second GAA-FET provided on said substrate and comprising a second channel having a trimmed volume of second channel material which is less than said untrimmed volume of first channel material by a predetermined trim amount corresponding to a delay adjustment of the second GAA-FET relative to the first GAA-FET, wherein said first and second GAA FETs are electrically connected as complementary FETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.