Vertically stacked devices with self-aligned regions formed by direct self assembly (DSA) processing
US10991696B2 · kind B2 · utility
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12Claims
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Key dates
| Filing date | Mar 15, 2017 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Mar 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An integrated circuit structure is provided which comprises: a stack of source regions of a stack of transistors and a stack of drain regions of the stack of transistors; and a gate stack that forms gate regions for the stack of transistors, wherein the gate stack comprises traces of a first polymer of a block copolymer, the block copolymer comprising the first polymer and a second polymer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.