Structure and formation method of semiconductor device structure with nanowires
US10991811B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2019 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Aug 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a plurality of nanowires over an input-output region, and a protective layer surrounding the nanowires. The protective layer is made of silicon, silicon germanium, silicon oxide, silicon nitride, silicon sulfide, or a combination thereof. The semiconductor device structure also includes a high-k dielectric layer surrounding the protective layer, and a gate electrode surrounding the high-k dielectric layer. The semiconductor device structure further includes a source/drain portion adjacent to the gate electrode, and an interlayer dielectric layer over the source/drain portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.