Fabrication of multi-channel nanowire devices with self-aligned internal spacers and SOI FinFETs using selective silicon nitride capping
US10998423B2 · kind B2 · utility
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Key dates
| Filing date | May 22, 2020 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | May 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of selectively nitriding surfaces of semiconductor devices are disclosed. For example, a hardmask is formed on the top portion of the fins to create SOI structure. The hardmask may be formed by nitriding the top portion of the fin. In other embodiments, silicon nitride is grown on the top portion of the fin to form the hard masks. In another example, internal spacers are formed between adjacent nanowires in a gate-all-around structure. The internal spacers may be formed by nitriding the remaining interlayer material between the channel region and source and drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.