Patent · US Active

Method, system and device for integration of bitcells in a volatile memory array and bitcells in a non-volatile memory array

US11004479B2 · kind B2 · utility

3Cited by

34References

20Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Mudit Bhargava · Austin, US
Shidhartha Das · Cambourne, GB
George McNeil Lattimore · Austin, US
Brian Tracy Cline · Austin, US

Key dates

Filing date	Mar 27, 2020
Grant date	May 11, 2021
Priority date	—
Expiry date	Mar 27, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG11C2207/2263
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.