Recessed STI as the gate dielectric of HV device
US11004844B2 · kind B2 · utility
1Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2018 |
| Grant date | May 11, 2021 |
| Priority date | — |
| Expiry date | Aug 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0142
Abstract
A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.