Memory layout structure
US11011210B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2019 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Dec 25, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory layout structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with all storage units on a corresponding active area, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.