Semiconductor package
US11011502B2 · kind B2 · utility
4Cited by
4References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 8, 2019 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Jan 8, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first package including a first semiconductor chip, a first encapsulation layer that covers the first semiconductor chip, and a first redistribution pattern connected to pads of the first semiconductor chip and a second package on the first package, the second package including a second semiconductor chip, a second encapsulation layer that covers the second semiconductor chip, and a second redistribution pattern connected to pads of the second semiconductor chip. The first redistribution pattern is connected to the second redistribution pattern through the first encapsulation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.