Semiconductor structure patterning

US11011521B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Sevim Korkmaz · Boise, US
• Devesh Dadhich Shreeram · Boise, US
• Srinivasan Balakrishnan · Bengaluru, IN
• Dewali Ray · Boise, US
• Sanjeev Sapra · Boise, US
• Paul A. Paduano · Boise, US

Key dates

• Filing date: May 28, 2019
• Grant date: May 18, 2021
• Expiry date: May 28, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/714

Abstract

Methods, apparatuses, and systems related to removing a hard mask are described. An example method includes patterning a silicon hard mask on a semiconductor structure having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes an opening through the semiconductor structure using the patterned hard mask to form a pillar support. The method further includes forming a silicon liner material on the semiconductor structure. The method further includes removing the silicon liner material using a wet etch process.