Memory cell, nonvolatile semiconductor storage device, and method for manufacturing nonvolatile semiconductor storage device
US11011530B2 · kind B2 · utility
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6Claims
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Key dates
| Filing date | Jun 7, 2019 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Jun 7, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.