Vertical interconnect methods for stacked device architectures using direct self assembly with high operational parallelization and improved scalability

US11011537B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Aaron D. Lilak · Beaverton, US
• Patrick Theofanis · Pasadena, US
• Patrick Morrow · Portland, US
• Rishabh Mehandru · Portland, US
• Stephen M. Cea · Hillsboro, US

Key dates

• Filing date: Sep 30, 2016
• Grant date: May 18, 2021
• Expiry date: Nov 18, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/35

Abstract

An apparatus including an array of at least two vertically stacked layers of integrated circuit device components separated by a dielectric layer on a substrate, wherein each of the at least two vertically stacked layers includes a laterally disposed contact point; and an electrically conductive interconnection coupled to a lateral edge of the contact point of each of the at least two vertically stacked layers and bridging the dielectric layer. A method including forming an array of at least two vertically stacked layers of integrated circuit device components separated by a dielectric layer on a substrate, forming a trench that exposes a lateral contact point of each of the at least two vertically stacked layers; depositing a polymer in the trench, wherein the polymer preferentially aligns to a material of the lateral contact point and bridges the dielectric layer; and modifying or replacing the polymer with an electrically conductive material.