Formation of a partial air-gap spacer
US11011617B2 · kind B2 · utility
3Cited by
7References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2018 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | May 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is presented for reducing parasitic capacitance. The method includes forming multi-layer spacers between source/drain regions, forming a dielectric liner over the multi-layer spacers and the source/drain regions, forming gate structures adjacent the multi-layer spacers, forming a self-aligned contact cap over the gate structures, and removing a sacrificial layer of each of the multi-layer spacers to form air-gaps between the gate structures and the source/drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.