Cascade streaming between data processing engines in an array
US11016822B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2018 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Nov 13, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples herein describe techniques for communicating directly between cores in an array of data processing engines. In one embodiment, the array is a 2D array where each of the data processing engines includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the cores. Using the interconnect, however, can add latency when transmitting data between the cores. In the embodiments herein, the array includes core-to-core communication links that directly connect one core in the array to another core. The cores can use these communication links to bypass the interconnect and the memory module to transmit data directly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.