Jan Langer
27Patents
6h-index
22Co-inventors
65Inventor score
Filing activity: Mar 5, 2013 → Feb 27, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10747690B2 | Device with data processing engine array | Electricity | 19 | Active |
| US10866753B2 | Data processing engine arrangement in a device | Physics | 15 | Active |
| US10824584B1 | Device with data processing engine array that enables partial reconfiguration | Physics | 13 | Active |
| US11336287B1 | Data processing engine array architecture with memory tiles | Electricity | 12 | Active |
| US9189458B1 | Parameter estimation | Electricity | 10 | Active |
| US11520717B1 | Memory tiles in data processing engine array | Physics | 6 | Active |
| US10635622B2 | System-on-chip interface architecture | Physics | 6 | Active |
| US11669464B1 | Multi-addressing mode for DMA and non-sequential read and write patterns | Physics | 5 | Active |
| US10990552B1 | Streaming interconnect architecture for data processing engine array | Physics | 3 | Active |
| US11113223B1 | Dual mode interconnect | Emerging Cross-Sectional Technologies | 3 | Active |
| US11323391B1 | Multi-port stream switch for stream interconnect network | Emerging Cross-Sectional Technologies | 2 | Active |
| US11379389B1 | Communicating between data processing engines using shared memory | Physics | 1 | Active |
| US11016822B1 | Cascade streaming between data processing engines in an array | Physics | 1 | Active |
| US10747531B1 | Core for a data processing engine in an integrated circuit | Physics | 1 | Active |
| US11372803B2 | Data processing engine tile architecture for an integrated circuit | Physics | 0 | Active |
| US12105667B2 | Device with data processing engine array that enables partial reconfiguration | Physics | 0 | Active |
| US11599498B1 | Device with data processing engine array that enables partial reconfiguration | Physics | 0 | Active |
| US11296707B1 | Data processing engine array architecture with memory tiles | General | 0 | Revoked |
| US11972132B2 | Data processing engine arrangement in a device | Physics | 0 | Active |
| US11573726B1 | Data processing engine arrangement in a device | Physics | 0 | Active |
| US11567881B1 | Event-based debug, trace, and profile in device with data processing engine array | Physics | 0 | Active |
| US11730325B2 | Dual mode interconnect | Emerging Cross-Sectional Technologies | 0 | Active |
| US11443091B1 | Data processing engines with cascade connected cores | Physics | 0 | Active |
| US11853235B2 | Communicating between data processing engines using shared memory | Physics | 0 | Active |
| US11061673B1 | Data selection network for a data processing engine in an integrated circuit | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.