Efficient projection based adjustment evaluation in static timing analysis of integrated circuits
US11017137B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2019 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Oct 7, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The efficiency of electronic design automation is increased by building, as an electronic data structure, a timing graph characterizing a putative integrated circuit design; identifying at least one of an edge and a node in the timing graph that requires canonical timing adjustment; and electronically calculating a deterministic timing adjustment for each of a plurality of corner cases. Based on the calculated deterministic timing adjustment for each of the plurality of corner cases, the canonical timing adjustment is determined for the at least one of an edge and a node; the canonical timing adjustment is applied to the timing graph; and the timing graph is updated based on the application of the canonical timing adjustment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.