Timing analysis for parallel multi-state driver circuits
US11017138B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2020 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Apr 6, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) includes multiple interconnected driver cells enabled/disabled based on a first set of control signals. The multiple circuit cells are arranged to define a first aggregate enabled/disabled configuration exhibiting a first aggregated delay. The first aggregated delay is based on the individual enabled/disabled states of the circuit cells. Timing circuitry evaluates the first aggregate delay with respect to a circuit design constraint, and selectively generates a second set of control signals to configure the multiple circuit cells to define a second aggregate enabled/disabled configuration having a second aggregate delay different than the first aggregate delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.