Soft reset for multi-level programming of memory cells in non-Von Neumann architectures
US11017856B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2020 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Feb 18, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for setting memory elements in a plurality of states includes applying a set signal to a memory element to transition the memory element from a low-current state to a high-current state; applying a partial reset signal to the memory element to transition the memory element from the high-current state to a state between the high-current state and the low-current state; determining whether the state corresponds to a predetermined state; and applying one or more additional partial reset signals to the memory element until the state corresponds to the predetermined current state. The memory element may be coupled in series with a transistor, and a voltage control circuit may apply voltages to the transistor to set and partially reset the memory element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.