Integrated circuit structure
US11018103B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2019 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Oct 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure includes a substrate, a metal pad, a first passivation layer, a second passivation layer, and a conductive bump. The metal pad is over the substrate. The metal pad includes a probing portion and a bumping portion laterally connected to the probing region. The first passivation layer is over the metal pad. The second passivation layer is over the first passivation layer and has an opening. The bumping portion is in the opening. The conductive bump is in the opening of the second passivation layer and contacts the probing portion. The probing portion and the conductive bump are separated by the first passivation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.