Patent · US Active

Monolithic silicon bridge stack including a hybrid baseband die supporting processors and memory

US11018114B2 · kind B2 · utility

0Cited by

2References

25Claims

0Family size

Assignee

Intel IP Corporation · US

Inventors

Bernd Waidhas · Nittendorf, DE
Georg Seidemann · Landshut, DE
Andreas Augustin · Munich, DE
Laurent Millou · Munich, DE
Andreas Wolter · Regensburg, DE
Reinhard Mahnkopf · Oberhaching, DE
Stephan Stoeckl · Schwandorf, DE
Thomas Wagner · Regelsbach, DE

Key dates

Filing date	Jul 18, 2019
Grant date	May 25, 2021
Priority date	—
Expiry date	Jul 18, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2225/1058
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.