Methods for forming device isolation for semiconductor applications
US11018223B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2019 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Jul 3, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/371
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provide methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes forming a multi-material layer on a bottom structure on a substrate, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, selectively removing the second layer from the multi-material layer from the substrate, and selectively oxidizing the bottom structure on the substrate after removing the second layer from the multi-material layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.