Double-load instruction using a fixed stride and a variable stride for updating addresses between successive instructions
US11023239B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2019 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Apr 19, 2039 |
Classification
- Technology area (CPC —)General
Abstract
A processor comprising an execution unit, memory and one or more register files. The execution unit is configured to execute instances of machine code instructions from an instruction set. The types of instruction defined in the instruction set include a double-load instruction for loading from the memory to at least one of the one or more register files. The execution unit is configured so as, when the load instruction is executed, to perform a first load operation strided by a fixed stride, and a second load operation strided by a variable stride, the variable stride being specified in a variable stride register in one of the one or more register files.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.