Multiple sense amplifier and data path-based pseudo dual port SRAM
US11024347B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2019 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Oct 17, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory array of memory cells, wordlines and bitlines connected to the memory cells, a first read multiplexor and a second read multiplexor connected to the bitlines, a first sense amplifier connected to the first read multiplexor, a second sense amplifier connected to the second read multiplexor, a first data path connected to the first sense amplifier, and a second data path connected to the second sense amplifier. Each of the memory cells is connected to only one pair of the bitlines and only one of the wordlines. The first read multiplexor is adapted to connect the first sense amplifier to the bitlines during a first portion of a clock cycle and the second read multiplexor is adapted to connect the second sense amplifier to the bitlines during a second portion of a clock cycle that is different from the first portion of the clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.