Read operation for non-volatile memory with compensation for adjacent wordline
US11024393B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2020 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Jan 9, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprises a driver circuit, sense circuit, and die controller. The driver circuit supplies a pass voltage to a selected word line and unselected word lines, a sense voltage to an adjacent word line, and a bit line voltage to bit lines coupled to selected and unselected word lines. The sense circuit determines nonconducting and conducting memory cells on the adjacent word line. The die controller then directs the driver circuit to ramp the sense voltage on the adjacent word line to the pass voltage and ramp the pass voltage on the selected word line to ground. The die controller then directs the driver circuit to ramp the bit line voltage for bit lines coupled to nonconducting memory cells to a bit line compensation voltage and directs the sense circuit to read memory cells of the selected word line based on the bit line compensation voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.