Inventor · Fujisawa, JP

Ken Oowada

67Patents
13h-index
51Co-inventors
83Inventor score

Filing activity: May 12, 2005 → Mar 2, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US8130551B2 Extra dummy erase pulses after shallow erase-verify to avoid sensing deep erased threshold voltage Physics 44 Active
US7355889B2 Method for programming non-volatile memory with reduced program disturb using modified pass voltages Physics 40 Expired
US7295478B2 Selective application of program inhibit schemes in non-volatile memory Physics 40 Expired
US8472257B2 Nonvolatile memory and method for improved programming with reduced verify Physics 31 Active
US7355888B2 Apparatus for programming non-volatile memory with reduced program disturb using modified pass voltages Physics 21 Expired
US8902668B1 Double verify method with soft programming to suppress read noise Physics 19 Active
US9214240B2 Dynamic erase depth for improved endurance of non-volatile memory Physics 18 Active
US8787088B2 Optimized erase operation for non-volatile memory with partially programmed block Physics 17 Active
US7447086B2 Selective program voltage ramp rates in non-volatile memory Physics 17 Active
US8582381B2 Temperature based compensation during verify operations for non-volatile storage Physics 15 Active
US7460404B1 Boosting for non-volatile storage using channel isolation switching Physics 15 Active
US8885420B2 Erase for non-volatile storage Physics 15 Active
US8218366B2 Programming non-volatile storage including reducing impact from other memory cells Physics 13 Active
US8953386B2 Dynamic bit line bias for programming non-volatile memory Physics 13 Active
US7995394B2 Program voltage compensation with word line bias change to suppress charge trapping in memory Physics 13 Active
US8743615B2 Read compensation for partially programmed blocks of non-volatile storage Physics 12 Active
US8908441B1 Double verify method in multi-pass programming to suppress read noise Physics 12 Active
US8885416B2 Bit line current trip point modulation for reading nonvolatile storage elements Physics 12 Active
US8929142B2 Programming select gate transistors and memory cells using dynamic verify level Physics 10 Active
US9123424B2 Optimizing pass voltage and initial program voltage based on performance of non-volatile memory Physics 10 Active
US8958249B2 Partitioned erase and erase verification in non-volatile memory Physics 10 Active
US9543023B2 Partial block erase for block programming in non-volatile memory Physics 9 Active
US9548130B2 Non-volatile memory with prior state sensing Electricity 8 Active
US7978527B2 Verification process for non-volatile storage Physics 8 Active
US8913432B2 Programming select gate transistors and memory cells using dynamic verify level Physics 8 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.