Memory system and operation method thereof
US11024402B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 8, 2020 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Apr 8, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system may include: an error correction code (ECC) generation circuit suitable for generating an M-bit error correction code using N-bit data, where N and M are positive integers; a memory core suitable for storing the N-bit data and the M-bit error correction code; and an ECC circuit suitable for correcting an error of the N-bit data read from the memory core, using the M-bit error correction code read from the memory core, wherein the ECC generation circuit generates the M-bit error correction code using an M×(N+M) check matrix, wherein one column vector among M column vectors corresponding to the M-bit error correction code in the M×(N+M) check matrix has an odd weight, and the other M column vectors have even weights.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.