Patent · US Active

Assembly for 3D circuit with superposed transistor levels

US11024544B2 · kind B2 · utility

0Cited by

0References

23Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

Francois Andrieu · Meylan, FR
Lamine Benaissa · Massy, FR
Laurent Brunet · Léguevin, FR

Key dates

Filing date	Dec 17, 2018
Grant date	Jun 1, 2021
Priority date	—
Expiry date	Dec 27, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/0177
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Fabrication of a circuit with superposed transistors includes assembly of a structure having transistors formed from a first semiconducting layer with a support provided with a second semiconducting layer in which transistors are provided on a higher level. The second semiconducting layer is coated with a thin layer of silicon oxide. The assembly of said structure and the support is made by direct bonding in which the thin silicon oxide layer is bonded to oxidised portions of getter material.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.