Metal replacement vertical interconnections for buried capacitance
US11024551B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2020 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Jan 7, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0186
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is presented for forming a multi-level of interconnects underneath a complementary metal oxide semiconductor (CMOS) device. The method includes forming a stack including alternating layers of a semiconductor material and a first conductive material, patterning vias in the stack to define multiple stacks, depositing a first block material within each of the vias, forming a series of first block materials within a first via, forming a series of second block materials within a second via, the first and second vias being on opposed ends of a stack of the multiple stacks, and performing vertical metallization between the first block material and the series of first block materials in the first via, and between the first block material and the series of second block materials in the second via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.