Self-aligned planarization of low-k dielectrics and method for producing the same
US11031251B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2019 |
| Grant date | Jun 8, 2021 |
| Priority date | — |
| Expiry date | Aug 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a uniform self-aligned low-k layer with a large process window for inserting a memory array with pillar/convex topography and the resulting device are provided. Embodiments include forming a substrate with a first region and a second region; forming a first low-K layer over the substrate; forming an oxide layer over the first low-K layer; forming a spacer over the oxide layer; etching the spacer to expose the oxide layer in the first region; removing the oxide layer and a portion of the first low-K layer in the first region and a portion of the oxide layer and a portion of the spacer in the second region; removing the spacer in the second region; cleaning the first low-K layer and the oxide layer, a triangular-like shaped portion of the oxide layer remaining; and forming a second low-K layer over the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.