Structures and methods for reducing process charging damages
US11031320B2 · kind B2 · utility
2Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2019 |
| Grant date | Jun 8, 2021 |
| Priority date | — |
| Expiry date | Nov 6, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.