Fins for enhanced die communication
US11031343B2 · kind B2 · utility
0Cited by
5References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2019 |
| Grant date | Jun 8, 2021 |
| Priority date | — |
| Expiry date | Jun 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor structures are provided in which a first chip on a substrate has at least one first protruding section, the first protruding section including first interconnect locations, a second chip on the substrate having at least one second protruding section, the second protruding section including second interconnect locations and the first chip and the second chip are arranged such that the first protruding section is interdigitated with the second protruding section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.