Spacer for die-to-die communication in an integrated circuit
US11031373B2 · kind B2 · utility
1Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2019 |
| Grant date | Jun 8, 2021 |
| Priority date | — |
| Expiry date | May 29, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19103
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-die integrated circuit device and a method of fabricating the multi-die integrated circuit device involve a substrate. Two or more dice include components that implement functionality of the multi-die integrated circuit. The components include logic gates. The multi-die integrated circuit device also includes a spacer disposed between the substrate and each of the two or more dice. Each of the two or more dice makes direct electrical contact with the substrate without making direct electrical contact with the spacer through holes in the spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.