Phase-change memory cell having a compact structure
US11031550B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 28, 2019 |
| Grant date | Jun 8, 2021 |
| Priority date | — |
| Expiry date | Jun 28, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.