Host-resident translation layer write command associated with logical block to physical address of a memory device
US11036625B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2020 |
| Grant date | Jun 15, 2021 |
| Priority date | — |
| Expiry date | Apr 24, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device in a memory system receives, from a host system, a host-resident translation layer write command requesting that data associated with a logical block address be written to the memory device and that a physical address to which the data is written be returned in response and performs a write operation to write the data associated with the logical block address to the physical address of the memory device. The processing device updates a translation layer entry corresponding to the logical block address to include the physical address and sends, to the host system, a response to the host-resident translation layer write command, the response comprising the updated translation layer entry with the physical address. The host system can to store the updated translation layer entry with the physical address in a host-resident translation layer mapping table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.