Combinatorial serial and parallel test access port selection in a JTAG interface

US11041905B2 · kind B2 · utility

Assignee

• STMicroelectronics International N.V. · NL

Inventors

• Venkata Narayanan Srinivasan · Greater Noida, IN
• Manish Sharma · Sunnyvale, US

Key dates

• Filing date: Nov 1, 2019
• Grant date: Jun 22, 2021
• Expiry date: Nov 1, 2039

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318558
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A circuit includes a test data input (TDI) pin receiving a test data input signal, a test data out (TDO) pin outputting a test data output signal, and debugging test access port (TAP) having a test data input coupled to the TDI pin and a bypass register having an input coupled to the test data input of the debugging TAP. A multiplexer has inputs coupled to the TDI pin and the debugging TAP. A testing TAP has a test data input coupled to the output of the multiplexer, and a data register having an input coupled to the test data input of the testing TAP. The multiplexer switches so the test data input signal is selectively coupled to the input of the data register of the testing TAP so the output of the debugging TAP is selectively coupled to the input of the data register of the testing TAP.