Memory management
US11042306B2 · kind B2 · utility
2Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 2019 |
| Grant date | Jun 22, 2021 |
| Priority date | — |
| Expiry date | May 23, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.