Semiconductor device with modified access and associated methods and systems
US11042436B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2019 |
| Grant date | Jun 22, 2021 |
| Priority date | — |
| Expiry date | Nov 17, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may access a group of memory cells (e.g., portion of an array configurable to store ECC parity bits) otherwise reserved for ECC functionality of a memory device. The memory device may include a register to indicate whether its ECC functionality is enabled or disabled. When the register indicates the ECC functionality is disabled, the memory device may increase a storage capacity available to the host device by making the group of memory cells available for user-accessible data. Additionally or alternatively, the memory device may store metadata associated with various operational aspects of the memory device in the group of memory cells. Moreover, the memory device may modify a burst length to accommodate additional information to be stored in or read from the group of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.