Circuit for detection of predominant data in a memory cell
US11043248B2 · kind B2 · utility
0Cited by
4References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 9, 2020 |
| Grant date | Jun 22, 2021 |
| Priority date | — |
| Expiry date | Jan 19, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Memory device comprising a matrix of memory cells, the matrix being provided with at least one first column, the device also being provided with a test circuit configured to perform a test phase during a read operation to indicate whether or not the proportion of cells in said column storing the same logical data, particularly a logical ‘1’, is greater than a predetermined threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.