Method and apparatus of package enabled ESD protection

US11043484B1 · kind B1 · utility

Assignee

• XILINX, INC. · US

Inventors

• Hong Shi · Fremont, US
• James Karp · Saratoga, US
• Siow Chek Tan · Los Gatos, US
• Martin L. Voogel · Los Altos, US
• Mohsen H. Mardi · Saratoga, US
• Suresh Ramalingam · Fremont, US
• David M. Mahoney · Palo Alto, US

Key dates

• Filing date: Mar 22, 2019
• Grant date: Jun 22, 2021
• Expiry date: Jun 5, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/15311
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Techniques for electrostatic discharge (ESD) protection in integrated circuit (IC) chip packages methods for testing the same are described that are configured to directs the risk of ESD events through ground and power interconnects preferentially over I/O interconnects to enhance ESD protection in chip packages. In one example, a chip package is provided that includes an IC die, a substrate, and a plurality of interconnects. The plurality of interconnects are exposed on a side of the substrate opposite the IC die. The interconnects provide terminations for substrate circuitry formed within the substrate. At least one of the last 5 interconnects of the plurality of interconnects respectively comprising rows and columns of interconnects disposed along the edges of the substrate that closest to each corner of substrate project farther from the substrate than interconnects within those rows and columns that are configured as I/O interconnects.