Fast-converging soft bit-flipping decoder for low-density parity-check codes
US11043969B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2019 |
| Grant date | Jun 22, 2021 |
| Priority date | — |
| Expiry date | Nov 12, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6331
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed are devices, systems and methods improving the convergence of a soft bit-flipping decoder in a non-volatile memory device. An example method includes receiving a noisy codeword, the codeword having been generated based on a parity check matrix of an LDPC code and provided to a communication channel prior to reception by the soft bit-flipping decoder, generating, based on the noisy codeword, one or more messages for passing between a plurality of variable nodes and a plurality of check nodes of the soft bit-flipping decoder, generating a reliability metric for each of the one or more messages, storing the reliability metric only for messages comprising magnitudes that are less than or equal to a predetermined threshold value; and performing, based on the one or more messages and the associated reliability metric for at least one of the one more messages, a single decoding iteration of the soft bit-flipping decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.