Path based controls for ATE mode testing of multicell memory circuit
US11047910B2 · kind B2 · utility
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9References
20Claims
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Key dates
| Filing date | Nov 9, 2018 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Nov 9, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test override circuit includes a memory that includes multiple memory instances. A path selector receives a control signal from automatic test pattern generator equipment (ATE) to control data access to data paths that are operatively coupled between the memory instances and a plurality of logic endpoints. The path selector generates an output signal that indicates which of the data paths is selected in response to the control signal. A gating circuit enables the selected data paths to be accessed by at least one of the plurality of logic endpoints in response to the output signal from the path selector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.